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[VHDL-FPGA-Verilog] Verilog_sdram

Description: Verilog写的SDRAM接口控制资料希望对大家有用！-Verilog write SDRAM interface control information for all of us hope!
Platform: | Size: 23552 | Author: 倔强 | Hits:

[VHDL-FPGA-Verilog] pudn

Description: VHDL写的SDRAM的精简控制器。包含SDRAM接口控制器，和数据读写控制。含有实际抓取的signatap波形。为初学SDRAM者的，最好参考。-A SDRAM controller written in VHDL.Including SDRAM interface controller, read and write control. It is the best reference for SDRAM learners .
Platform: | Size: 142336 | Author: 邓奇勋 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 用Verilog写的SDRAM的控制器的代码，分为详细实现了对SDRAM的控制-Written using Verilog code for SDRAM controller is divided into in detail to achieve the control of SDRAM
Platform: | Size: 14336 | Author: feifei | Hits:

[VHDL-FPGA-Verilog] memtest

Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: | Size: 223232 | Author: 平凡 | Hits:

[Special Effects] lab_04

Description: SDRAM,FLASH存储器控制与驱动。编程实现DSP开发板相关接口与外设的初始化程序，读出及显示实验板上Flash 存储器中的图像。-SDRAM, FLASH memory control and drive. DSP development board programming interfaces and peripherals related to the initialization procedure, read the experiment on-board Flash memory and display the image.
Platform: | Size: 589824 | Author: 解娜 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design
Platform: | Size: 12288 | Author: zhangdong | Hits:

[Windows Develop] EXINT_module

Description: 本文件夹中的代码是“外部中断模块”的相应代码。 exint.c 该文件是EXINT代码，包括main主函数、中断服务程序等。 EXINT.pdf 该文件是C6713外部中断EXINT原理图，至于C6713的其他部分（如SDRAM、FLASH等）和部分控制信号、电源信号都略去。读者朋友可参考另外相关的章节。 -The code in this folder is " external interrupt module" of the corresponding code. exint.c the file is EXINT code, including the main the main function, the interrupt service program. EXINT.pdf the document is an external interrupt EXINT schematic C6713, C6713 For the rest (such as SDRAM, FLASH, etc.) and some control signals, power signals are omitted. Readers may refer to other relevant chapters.
Platform: | Size: 46080 | Author: 小胖 | Hits:

[Windows Develop] GPIO_module

Description: 本文件夹中的代码是“GPIO模块”的相应代码。 GPIO_LCM.c 该文件是GPIO模拟时序，实现SPI协议的代码。 GPIO.pdf 该文件是C6713的GPIO连接LED和LCM模块的原理图，至于C6713的其他部分（如SDRAM、FLASH等）和部分控制信号、电源信号都略去。读者朋友可参考另外相关的章节。 -The code in this folder is " GPIO module" of the corresponding code. GPIO_LCM.c GPIO analog timing of the document is to achieve SPI protocol code. GPIO.pdf the file is the GPIO connection C6713 LED and LCM module schematic, as in other parts of C6713 (such as SDRAM, FLASH, etc.) and some control signals, power signals are omitted. Readers may refer to other relevant chapters.
Platform: | Size: 48128 | Author: 小胖 | Hits:

[Embeded-SCM Develop] HPI_module

Description: 本文件夹中的代码是“HPI模块”的相应代码。 HPI.c 该文件是操作HPI的代码，包括HPI读写操作（地址固定或者自增模式）。 电路图.pdf 该文件是HPI和S3C44B0X的电路连接原理图，本电路图注重于描述主机CPU（即ARM芯片S3C44B0）和C6713间的HPI连接方式，所以，电路连接标号一般只涉及ARM、C6713之间的连接关系，至于C6713的其他部分（如SDRAM、FLASH等）和部分控制信号、电源信号都略去。读者朋友可参考另外相关的章节。-The code in this folder is " HPI module" of the corresponding code. HPI.c the file is HPI operation code, including HPI read and write operation (address fixed or self-growth model). Circuit. Pdf files are HPI and S3C44B0X the circuit connection diagram, circuit diagram focusing on the description of the main CPU (the ARM chip S3C44B0) and C6713 connection between the HPI, therefore, the circuit connection label generally involve ARM, C6713 between connection relations, as in other parts of C6713 (such as SDRAM, FLASH, etc.) and some control signals, power signals are omitted. Readers may refer to other relevant chapters.
Platform: | Size: 60416 | Author: 小胖 | Hits:

[VHDL-FPGA-Verilog] sdram_hr_hw

Description: SDRAM 读写控制检测Verilog源代码程序。-SDRAM read and write Verilog source code control testing procedures.
Platform: | Size: 102400 | Author: zhouxiao | Hits:

[VHDL-FPGA-Verilog] SDRAMcontrollerdesignl

Description: The SDRAM Controller module makes you control SDRAM conveniently with easy interface input type
Platform: | Size: 411648 | Author: phwer01 | Hits:

[VHDL-FPGA-Verilog] CPLD_V105

Description: epm240系列cpld的配置文件，实现cpld对flash，uart和sdram的控制等-epm240 series cpld profile, to achieve cpld on the flash, uart and the sdram of the control
Platform: | Size: 309248 | Author: 张枫 | Hits:

[matlab] DM642EDMA

Description: This program uses the timers to trigger EDMA events. These events in turn * trigger linked EDMA parameter tables to fill a ping pong buffer structure. * Set a breakpoint on swiProcessFunc(int arg). Then open two memory windows. * Use ping as the address for one memory window and pong for the other. Then * run the application. You ll note that the program bounces between the ping * and pong buffers filling each with a value that comes from the source. The * source in this case is the SDRAM timer control register and it simulates * input data-This program uses the timers to trigger EDMA events. These events in turn* trigger linked EDMA parameter tables to fill a ping pong buffer structure.* Set a breakpoint on swiProcessFunc (int arg). Then open two memory windows.* Use ping as the address for one memory window and pong for the other. Then* run the application. You' ll note that the program bounces between the ping* and pong buffers filling each with a value that comes from the source. The* source in this case is the SDRAM timer control register and it simulates* input data
Platform: | Size: 138240 | Author: 于海艳 | Hits:

[Other Embeded program] 3

Description: 键盘实验 本实验采用了直连键盘（1~4）对LED数码管进行控制。当按1键的时候，LED1数码管就会亮，同理，按相应的键，相应的数码管就会亮。 在flash调试时，需要修改RO BASE为0x00000000，其他不用修改，重新编译下载就可运行。 在sdram调试时，需要修改RO BASE为0xa0000000，其他不用修改，重新编译下载就可运行。-Experimental The experiment used the keyboard directly connected keyboard (1 ~ 4) LED digital tube control. When you press a button when, LED1 will light the digital control, empathy, press the appropriate key, the corresponding digital control will be bright. Debug in flash, you need to modify the RO BASE is 0x00000000, the other not modify, recompile download can run. Debugging in the sdram when the need to modify the RO BASE to 0xa0000000, others do not modify, recompile and download can be run.
Platform: | Size: 44032 | Author: | Hits:

[Other Embeded program] 5

Description: 定时器实验： 实验得到的结果为，四个8段数码管显示1234，当按下某键盘后，就会产生定时中断，四个8段数码管只会点亮相对应的那个，在一定延时后，四个8段数码管又恢复显示1234。 在flash调试时，需要修改RO BASE为0x00000000，其他不用修改，重新编译下载就可运行。 注意：由于系统产生中断，程序计数器就会跳到0x18处执行中断服务子程序，所以不能在SDRAM调试。 -Timer experiment: the experimental results for the four 8-segment LED display 1234, when the press of a keyboard, the timer interrupt will be generated, four 8 point digital control will appear that corresponds to a certain delay After four 8 digital tube display resumed 1234. Debug in flash, you need to modify the RO BASE is 0x00000000, the other not modify, recompile download can run. Note: Due to system interrupt, the program counter will jump to 0x18 Department execute the interrupt service routine, it can not debug the SDRAM.
Platform: | Size: 45056 | Author: | Hits:

[Com Port] 6

Description: 串口通讯实验： 本实验得到的结果为，打开超级终端，设置波特率为115200，数据流控制位为无。运行系统，就会显示“UART & Interrupt Experiment,Please Input from the keyboard”，我们就可以通过写串口操作。 在flash调试时，需要修改RO BASE为0x00000000，其他不用修改，重新编译下载就可运行。 注意：由于系统产生中断，程序计数器就会跳到0x18处执行中断服务子程序，所以不能在SDRAM调试。 -Serial communication experiment: the results of this experiment, open HyperTerminal, set the baud rate to 115200, data flow control bit is not. Operating system, it will display " UART & Interrupt Experiment, Please Input from the keyboard" , we can write the serial port operation. Debug in flash, you need to modify the RO BASE is 0x00000000, the other not modify, recompile download can run. Note: Due to system interrupt, the program counter will jump to 0x18 Department execute the interrupt service routine, it can not debug the SDRAM.
Platform: | Size: 83968 | Author: | Hits:

[VHDL-FPGA-Verilog] SDRAMcontrol

Description: 用VHDL编写的SDRAM控制器，能实现SDRAM的读写控制及片选。-Prepared using VHDL SDRAM controller, able to SDRAM read and write control and chip select.
Platform: | Size: 1031168 | Author: 曾强 | Hits:

[VHDL-FPGA-Verilog] sdr_verilog_lattice

Description: Verilog控制SDRAM-Verilog control SDRAM
Platform: | Size: 18432 | Author: linhai | Hits:

[DSP program] SdramTest

Description: 该工程为DM642对SDRAM芯片MT48LC4M32的读写控制程序，可以用来作为SDRAM芯片的测试程序-The project for the DM642 to read and write to the SDRAM chip MT48LC4M32 control procedures that can be used as the SDRAM chip test program
Platform: | Size: 135168 | Author: 杨毅 | Hits:

[VHDL-FPGA-Verilog] SDRAM1

Description: 这是一个控制sdram的程序，用verilog编写的-This is a control program sdram, prepared with verilog
Platform: | Size: 4651008 | Author: 陈宇 | Hits:
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